SoC Chip Architect, Google Cloud, Silicon

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

As an SoC Chip Architect at Google Cloud, you will lead the definition of groundbreaking, high-performance custom silicon and multi-chiplet systems for Google Cloud AI infrastructure. You will bridge the gap between hyperscale data center workload requirements and silicon implementation across various domains, collaborating with cross-functional partners to design scalable, energy-efficient, and feature-rich SoCs.

You will be part of a team pushing the boundaries of custom silicon engineering, architecting next-generation data center products that deliver industry-leading performance, low latency, and massive bandwidth for Google Cloud and Google's flagship AI services. The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're behind Google's groundbreaking innovations, empowering the development of AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Responsibilities

• Lead top-level SoC architecture across multiple disciplines, including IP architects, digital design, verification, physical design, validation, firmware, power management, security, and system software. • Architect and analyze complex multi-chiplet systems, including chip partitioning, die-to-die (D2D) interconnects, advanced packaging constraints, and high-performance on-chip fabrics (NoC). • Define top-level SoC subsystems, memory hierarchies, clock distribution, reset schemes, and power domains to ensure optimal system performance and operational efficiency. • Formulate end-to-end operational flows, latency models, and system throughput analyses for data center workloads. • Own the SoC architecture specification and lead it throughout the complete product life-cycle: concept, modeling, implementation, tape-out, and post-silicon bring-up.

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, or equivalent practical experience. • 15 years of experience leading the architectural definition of high-performance SoCs, ASICs, or multi-chiplet systems from concept through production. • Experience architecting SoC interconnects, memory hierarchies, and system-level fabrics. • Experience writing, owning and maintaining comprehensive SoC architecture specifications. • Experience working across hardware, firmware, and system software boundaries with system-level reasoning.

Preferred qualifications:

• Master’s degree or PhD in Electrical Engineering or Computer Engineering. • Experience with AI workload analysis, their mapping across different data center system components, and optimizing hardware solutions to better serve them. • Experience scaling and optimizing high-performance AI accelerators, compute chiplets, or IO Hub SoCs for data center/cloud deployments. • Proven track record of architecting multi-chiplet systems utilizing cutting-edge silicon process technology and advanced packaging (2.5D/3D, D2D interfaces such as UCIe, BoW, or high-speed SerDes).