ASIC Digital Design, Sr Staff Engineer - 18576

General Information

Job Title

Sr. Staff Digital Verification Engineer (Memory Interface IP- HBM/DDR/LPDDR)

Job ID

18576

Country

India

City

Hyderabad

Date Posted

01-Sep-2026

Job Category

Engineering

Job Subcategory

ASIC Digital Design

Hire Type

Employee

Remote Eligible

No

Descriptions & Requirements

Job Description and Requirements

Job Title:

• Sr. Staff Digital Verification Engineer (Memory Interface IP- HBM/DDR/LPDDR)

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent the better part of a decade verifying complex ASIC designs, and you know that the hardest bugs are the ones that hide in corner cases three layers deep in a protocol handshake. You have worked on memory interfaces long enough to know that HBM, DDR, and LPDDR are not just acronyms, they are ecosystems with timing constraints, power states, and failure modes that can sink a tapeout if you miss them.

You do not wait for a design to be "ready" before you start thinking about verification. You are already mapping out testbenches, coverage models, and corner cases while the RTL is still being written. When something does not make sense in a spec, you ask. When a test fails in a way that should not be possible, you dig until you find the root cause, not just a workaround.