CPU Architecture and RTL Design Engineer

ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And we’re looking for talent who feel the same: people who want to leave the planet better than they found it, those who don’t shy away from humanity’s challenges but are determined to help solve them.

AMD is powering the next generation of supercomputing, high-performance computing, cloud, and AI. Whether you’re designing next-gen processors, enabling AI breakthroughs, or creating go-to-market plans, every role at AMD contributes to something bigger — technology that moves the world forward.

T HE ROLE :

As a CPL (Chip Pervasive Logic) CPU Architect/RTL Design Engineer , you will have an outstanding opportunity to drive the definition, implementation (RTL design), and integration of Clocking, Reset and Power in AMD’s next-generation caches/core. You will work as part of an experienced, skilled, and motivated engineering team with a track record of success. You will help make AMD’s ambitious future CPU roadmap a reality while working in a highly collaborative environment at the cutting edge of technology.

THE PERSON:

You approach challenges relentlessly with both critical thinking and creativity. You work as part of a team with strong communication and collaboration skills. You have a proven understanding of modern CPU architecture and have ideas and/or drive to make it even better. Does this describe you? If so, then join us

K EY RESPONSIBLITIES :

• Collaborate with a dedicated team of engineers to define and implement CPL microarchitecture for AMD CPUs. • Reliably deliver a design from concept through tapeout by innovating through complex and challenging requirements. • Drive design closure gaining experience with Static Timing, CDC/Gate CDC, and Static Power analysis. • Identify customer challenges and insert a compelling AMD value proposition to address challenges. • Make technical contributions and innovations that enable high performance, high frequency, and power efficiency on caches, fabrics, and interfaces of our server, desktop, and laptop CPUs.

P REFERRED EXPERIENCE :

• Proficiency with Verilog HDL, Clock/Power Domain Crossing concepts, and Power Management concepts. • Understanding of modern CPU architecture - prior experience designing shared cache or last level cache and related IPs a plus. • Eagerness to learn and grow as a CPL design engineer. • Collaborate effectively towards the success of the project by working closely with logic design, physical design and verification teamates across the wider organization. • Demonstrate a responsive track record of engaging with a diverse set of teams and across a broad set of technical areas to facilitate design delivery.