Graphics System-on-Chip
About this role
Company:
QUALCOMM SEMICONDUCTORES Y SISTEMAS AVANZADOS DE BAJA CALIFORNIA
Job Area:
Engineering Group, Engineering Group > ASICS Engineering
General Summary:
Qualcomm’s Global SoC Hardware team develops innovative products across advanced compute and connectivity. We are expanding our team in Tijuana and seeking engineers to help develop next-generation technologies for high-performance computing, AI, mobile, auto.
If you have the following skills/background (or have a deep interest!) we'd love to consider you!
ASIC Design Engineer
Contribute to ASIC and SoC development across architecture, RTL design, implementation, timing analysis, methodology, automation, and silicon bring-up.
Potential responsibilities:
• Develop ASIC/SoC architectures and RTL designs. • Support synthesis, constraints, STA, and timing closure. • Work on low-power and multi-voltage designs. • Develop design flows, automation, and tools. • Support IP integration, verification, simulation, and silicon bring-up.
SoC Design Verification Engineer
Ensure the quality and functionality of complex SoC designs through comprehensive verification, coverage, automation, and debug.
Key responsibilities:
• Develop verification plans and SystemVerilog/UVM environments. • Create directed and constrained-random tests, assertions, coverage models, and checkers. • Debug RTL, testbench, and integration issues. • Drive functional and code coverage closure. • Support emulation and acceleration-based verification. • Apply Automation and AI-assisted verification solutions
Physical Design Engineer
Drive physical implementation for advanced, high-speed, and low-power ASIC and SoC products.
Key responsibilities:
• Execute the physical design flow from netlist through tape-out. • Perform floorplanning, power planning, placement, CTS, routing, and timing closure. • Resolve timing, signal integrity, crosstalk, power, and design-rule issues. • Support extraction, physical verification, ECOs, and sign-off. • Develop low-power methodologies and design automation tools. • Collaborate with architecture, RTL, DFT, verification, and methodology teams.