ASIC Verification Engineer

What You'll Do

It used to be that high-speed packet forwarding was performed in dedicated ASIC designs. These days we are looking to make those ASICs more general and programmable. Cisco Common ASIC Group is looking for a Verification Engineer to drive existing projects and engage in new development of our next generation switching systems.

As part of ASIC team, you will be developing the ASICs at the heart of each of these switch products. There are only a very few teams worldwide that implement such devices. Every time you access the Internet, chances are, your data's been through one of our switches.

Who You'll Work With

You will work with Cisco’s best-in-class switching solution team. Our team is responsible for driving integration of the Nexus systems and ACI with software, including OpenStack, Docker, and Open vSwitch, to help our customers build multitenant clouds.

Who You Are

You are a talented, motivated ASIC verification engineer to join the team and contribute to the verification of very complex ASICs. You will have a Design Verification background, hands-on experience in System Verilog and UVM methodology, with basic knowledge of C++, scripting, as well as ASIC design and verification flow.

You’ll be part of Cisco Common ASIC Group, focusing on developing various test benches and contributing to different aspects of verification infrastructure.

You will collaborate closely with the design team and the hardware team to verify the ASIC in simulation, in emulation and during ASIC bring up.

Responsibilities Include:

• Designing UVM/SystemVerilog testbenches. • Defining new DV methodologies. • Enhancing existing testbenches. • End-to-end verification of various design blocks. • Contributing to top level verification. • Be a part of emulation testing efforts. • Participate in the ASIC bring-up

Education and Experience Required:

• Bachelor’s or master’s degree in EE and CE. • 3+ years of ASIC Design Verification

Knowledge and Skills:

• Collaborative and team-focused, with the drive to learn and grow • Hands-on experience on System Verilog and UVM methodology • Ability to construct testbench including scoreboard, agents, sequencers, and monitors • Ability to debug issues independently • Good Scripting experience (Python, Perl, TCL, shell programming) is a plus • Proficient in constrained random DV environments • Good written and verbal communication skills • Knowledge on latest high speed Ethernet protocol and packets is a plus.