Senior Staff / Principal Engineer, AMS Verification

We are seeking an AMS Verification Engineer to lead verification of the digital content embedded within power, analog, and mixed-signal IC products. This is a senior individual-contributor role requiring ownership of verification architecture, methodology, execution, and sign-off at block and full-chip level.

The successful candidate will build scalable verification environments from specifications, develop verification plans and coverage strategies, and verify control, protection, diagnostics, communication, trimming, test, and safety-related digital functions that interact closely with analog circuitry.

You will be expected to work autonomously, resolve ambiguous specification issues, establish verification flows from scratch where required, mentor engineers, and provide clear evidence that the design meets functional and product requirements before tape-out.

Responsibilities

Verification Strategy & Ownership

• Own block-level and full-chip digital verification strategy for power, analog, and mixed-signal IC products. • Develop verification plans from product and design specifications, including feature extraction, test intent, coverage goals, assumptions, and sign-off criteria. • Decompose complex functions into reusable verification components and scalable environments. • Identify specification gaps and drive closure with architecture, analog design, digital design, applications, and test teams.

Environment Development & Execution

• Design and develop SystemVerilog/UVM-based testbenches, agents, scoreboards, reference models, assertions, sequences, and coverage models. • Set up verification flows from scratch where needed and own regression execution, triage, debug, and closure. • Apply simulation, assertion-based verification, formal verification, and FPGA or emulation techniques where they provide practical value. • Verify digital behavior across reset, clock, power-state, fault, trim, communication, test-mode, and analog-interaction scenarios.

Mixed-Signal, DFT & Post-layout Support

• Collaborate with analog and digital teams to define appropriate models and verify analog-digital interactions at the required abstraction level. • Support DFT verification, scan and ATPG-related checks, production-test vector development, and test-mode verification. • Support gate-level simulation, timing-aware verification, and post-layout verification where required. • Contribute to silicon bring-up, device evaluation, root-cause analysis, and documented workarounds for device errata.