Director High Speed IO Architecture & Design

ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.

Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career.

T HE ROLE:

Lead a Hardware/Digital IP Design Engineering team, collaborating across AMD and partner to develop next-generation high-speed I/O technologies.

THE PERSON:

An experienced semiconductor IP leader with strong technical and managerial expertise, exceptional communication skills, and a proven ability to lead high-performing engineering teams.

KEY RESPONSIBILITIES:

• Provide technical leadership and direction for the hardware/digital semiconductor design engineering organization. • Lead and manage a team of System, Digital hardware, front-end/RTL/logic designers. • Manage and scale the design team to develop reusable IP supporting a multi products roadmap • Collaborate with IP. Sub-System, and SoC architects to translate high-level requirements into microarchitecture and design implementation plans. • Contribute to the definition of IP architecture & microarchitecture, circuit architecture, and digital subsystem blocks. • Drive architectural decisions for next-generation products within committed system-architecture and power, performance, and area budgets. • Represent the digital design organization in cross-functional architecture reviews, customer technical engagements, and foundry and EDA partner discussions. • Mentor front-end digital designers and micro architects through design reviews, technical coaching, and silicon debug. • Own high-level design planning, work breakdown, task assignment, progress tracking, schedule and priority management, performance reviews, talent development, and hiring. • Partners with the peer engineering directors, program managers, architects, circuit and AMS teams, and physical-design leads to deliver high-quality results on schedule and against technical requirements. • Proactively manages critical paths, dependencies, priorities, and overall program risk. • Collaborate across analog design, custom digital design, AMS circuit architecture, AMS design verification, functional verification, physical design, and DFX teams across multiple geographies. • Ensure strong cross-team alignment, engagement, and execution from architecture through production. • Co-lead the silicon-success methodology, establishing first-silicon-success expectations, disciplined debug practices, and a clear path from characterization to production. • Define and improve front-end development flows to increase execution efficiency, effectiveness, and quality. • Establish and enforce design-flow best practices and quality standards to meet committed performance, power, reliability, area, and timing requirements. • Work closely with physical-design and DFX teams to deliver complete RTL-to-GDSII designs. • Co-own post-silicon planning and execution, including initial bring-up, platform validation, characterization, parameter optimization, and final productization. • Contribute to IP production and bench-level test, characterization, and validation plans in partnership with post-silicon characterization and validation teams. • Enable and support post-silicon workstreams through new product introduction.